DVT - Design & Verification Tools

–  DVT is an IDE (Integrated Development Environment) for SystemVerilog, UPF/CPF. PSS, and VHDL.

–  On the fly standard compliant compilation, supporting various methodology in UVM (old OVM, VMM….are also supported)

–  Friendly environment for editing, Navigate and Search, lint, documentation..

–  DVT Debugger add-on module

•  It integrates with all major simulators and provides advanced debugging capabilities


–  SystemVerilog testbench linter


–  Documentation generator

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